1. Field of the Invention
The present invention relates to computer system memory, and in particular to systems and methods for implementing parallel data bus inversion.
2. Background of the Related Art
Digital memory systems store information in binary form using logical 0s and 1s. A digital memory system includes a driver to generate time-dependent voltage signals that represent the different logic levels. The logic levels are interpreted at a receiver according to the voltage values received. The voltage of a signal may be compared with a reference voltage at the receiver to determine which logic states are being represented at each instance of a clock signal. The reliability of the signal is dependent on the voltage margin between the signal and the reference voltage. Some amount of noise is typically present in the channel, which affects the signal voltage.
As computer technology advances, processor speeds continue to increase, creating a demand for faster memory systems capable of keeping pace with the increasing processor speeds. Faster memory bus speeds are facilitated, in part, by reducing the voltages of I/O data signals, to avoid excessive transition time from one signal level to another. However, reducing the signal voltage also reduces the voltage margin between the signal voltage and the reference voltage with which the signal is compared. If the magnitude of the fixed reference voltage is not suitable, then the available voltage margin may be inadequate and result in reduced signal reliability.
Double Data Rate (DDR) memory is susceptible to noise problems, such as Inter Symbol Interference (ISI) and Simultaneous Switching Output (SSO) noise, which can cause reduced voltage margins and corrupted data. Such noise problems may be caused, in part, by package, connector, and circuit board parasitics. The power consumption of a memory system is also affected by bus switching, which is the alternating voltages in the bus signal line changes as the voltage levels between values of 0 and 1. Present technologies to combat these problems include 8/10b encoding of packet based memory and parallel data bus inversion. Conventionally, these methods require hardware modifications to both DDR DRAM (double data rate, dual random access memory) chips and memory controllers.